High impedance connections in application specific integrated circuit (ASIC) attachments can cause system failures that are extremely difficult to debug. Many new connector systems (such as sockets for ball or land grid array packages) are especially susceptible to co-planarity problems, which result in new failure modes as compared to pin and socket connectors. These failure modes present significant challenges to the design and manufacture of high quality systems. Currently there is no way to predict and proactively deal with such failure modes, since such faults don't always manifest themselves as pure ‘opens,’ which, by nature, are much easier to detect.
The failure modes that result from high-impedance connections vary widely from easily detectable bus errors to completely unpredictable behavior. When these types of failure modes have been seen, the typical ‘solution’ has been to keep swapping boards until the system starts to work again. Debugging has been done by taking resistance measurements by hand (using an Ohm meter) to determine interconnect resistance. Unfortunately, this method is extremely time-consuming and, in many cases, results in an inaccurate reading. It is also something that occurs ‘after the fact.’ A more precise ‘in system’ approach is needed.